A. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a NOR-structured semiconductor memory device with a novel configuration of bit line connection.
B. Description of the Related Art
FIG. 1 is a schematic diagram showing a conventional NOR-structured semiconductor memory device 1. For the sake of descriptive simplicity, the conventional NOR-structured memory device 1 shown in FIG. 1 includes a 2xc3x978 memory cell array whose memory cells are electrically connected to corresponding word lines and bit lines. More specifically, the memory cells arranged in a row are electrically connected in parallel to a word line while the memory cells arranged in a column are electrically connected in parallel to two adjacent bit lines. For example, memory cells M10 to M17 are arranged in such a way that the gate electrodes of them are electrically connected in parallel to a word line WL1. Memory cells M10 and M00 are arranged in such a way that the channel electrodes (i.e., source and drain electrodes) of them are electrically connected in parallel to two adjacent bit lines BL0 and BL1, respectively.
Referring to FIG. 1, bit lines BL0 and BL2 are coupled to a main bit line MBL0 through bit line transistors BLT0 and BLT1, respectively. Bit lines BL1 and BL3 are coupled to a main bit line MBL2 through bit line transistors BLT4 and BLT5, respectively. The bit line transistors BLT0, BLT1, BTL4, and BLT5 may be N-type MOS (Metal-Oxide-Semiconductor) transistors and become conductive or non-conductive in response to selection signals input from selection lines SEL0, SEL1, SEL2, and SEL3, respectively. Similarly, bit lines BL4 and BL6 are coupled to a main bit line MBL1 through bit line transistors BLT2 and BLT3, respectively, while bit lines BL5 and BL7 are coupled to a main bit line MBL3 through bit line transistors BLT6 and BLT7, respectively. The bit line transistors BLT2, BLT3, BTL6, and BLT7 may be N-type MOS transistors and become conductive or non-conductive in response to selection signals input from selection lines SEL0, SEL1, SEL2, and SEL3, respectively.
The memory cells M00 to M07 and M10 to M17 may be programmable memory devices such as EPROM (Erasable Programmable Read Only Memory) or Flash EEPROM. In this case, the programming operation of a selected memory cell in the conventional NOR-structured memory device is described as follows. To program the memory cell M00 for example, the word line WL0 is activated and the selection lines SEL0 and SEL2 are activated to turn on the bit line transistors BLT0 and BLT4. In addition, the selection lines SEL1 and SEL3 are deactivated to turn off the bit line transistors BLT1 and BLT5. At the same time, the main bit line MBL2 is supplied with a high programming voltage and the main bit lines MBL0, MBL1, and MBL3 are all grounded. Therefore, the memory cell M00 is programmed through a current path L1 consisting of the main bit line MBL2, the bit line transistor BLT4, the bit line BL1, the bit line BL0, and the bit line transistor BLT0, and the main bit line MBL0.
During the programming operation of the memory cell M00, however, the memory cells M01, M02, M03, and M04 are simultaneously activated by the word line WL1 and subject to programming disturbance by the high programming voltage from the main bit line MBL2 since two other current paths L2 and L3 are formed as shown in FIG. 1. Therefore, it is desirable to provide a NOR-structured semiconductor memory device capable of preventing the programming disturbance during the programming operation.
There is also a problem in the conventional NOR-structured semiconductor memory device during the data reading operation. To read the data stored in the memory cell M00 for example, a sense current is supplied to the main bit line MBL2. If the memory cell M00 is turned off at the activation of the word line WL0, the potential of the main bit line MBL2 increases because no current path L1 is formed. Subsequently, the potential of the main bit line MBL2 is sensed and the data reading operation of the memory cell M00 is finished. During the data reading operation of the memory cell M00, however, the above-mentioned leakage current paths L2 and L3 as a result of the simultaneous activation of the memory cells M01, M02, M03, and M04 by the word line WL0 cause that it takes a longer time to raise the potential of the main bit line MBL2. In other words, it is difficult for a conventional NOR-structured semiconductor device shown in FIG. 1 to achieve high-speed data reading operations. In some cases, the leakage current paths L2 and L3 even make the sensed potential of the main bit line MBL2 become such a low value that the memory cell M00 is falsely determined as a turned-on cell. Therefore, it is desirable to provide a NOR-structured semiconductor memory device with high-speed data reading operations and correct data determinations.
In view of the above-mentioned problems of the conventional NOR-structured semiconductor memory device, it is an object of the present invention to provide a novel NOR-structured semiconductor memory device capable of preventing the programming disturbance during programming operations.
It is another object of the present invention to provide a novel NOR-structured semiconductor memory device with high-speed data reading operations.
It is still another object of the present invention to provide a novel NOR-structured semiconductor memory device in which the data stored in memory cells are correctly determined.
According to the present invention, a NOR-structured semiconductor memory device is provided with a semiconductor memory cell array having a plurality of semiconductor memory cells. The plurality of semiconductor memory cells may consist of programmable cells, such as EPROM or Flash EEPROM. A plurality of bit lines are electrically connected to the semiconductor memory cell array and divided into at least four bit line groups. At least two bit lines of each bit line group of the at least four bit line groups are coupled to a main bit line through at least two bit line transistors, respectively. The main bit line serves as a common main bit line for the coupled at least two bit lines. Furthermore, the bit lines of the NOR-structured semiconductor memory device are arranged in such a way that at least four adjacent bit lines thereof are selected from four different bit line groups and coupled to four different main bit lines, respectively.
During programming operations, two adjacent bit lines of the four adjacent bit lines are supplied with a programming voltage while the other two adjacent bit lines are grounded. Therefore, the NOR-structured semiconductor memory device according to the present invention successfully prevents the programming disturbance because no leakage current path is formed.
During data reading operations, two adjacent bit lines of the four adjacent bit lines are supplied with a sense current while the other two adjacent bit lines are grounded. Therefore, the NOR-structured semiconductor memory device according to the present invention correctly determines the data stored in memory cells at a high speed because no leakage current path is formed.